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applications ? medical imaging ? professional video ? radar receivers ? instrumentation ? electronic warfare ? digital communications spt7824 10-bit, 40 msps, ttl output a/d converter features ? monolithic 40 msps converter ? on-chip track/hold ? bipolar 2.0 v analog input ? 57 db snr @ 3.58 mhz input ? low power (1.0 w typical) ? 5 pf input capacitance ? ttl outputs signal processing technologies, inc. 4755 forge road, colorado springs, colorado 80907, usa phone: (719) 528-2300 fax: (719) 528-2370 analog prescaler 10 digital output successive interpolation stage i successive interpolation stage i+1 successive interpolation stage n analog input 4 coarse a/d t/h amplifier bank aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa decoding network indicate overflow conditions. output data format is straight binary. power dissipation is very low at only 1.0 watt with power supply voltages of +5.0 and -5.2 volts. the spt7824 also provides a wide input voltage swing of 2.0 volts. the spt7824 is available in 28-lead ceramic sidebrazed dip, pdip and soic packages over the c ommercial, industrial and military temperature ranges. consult the factory for availabil- ity of die and /833 versions. general description the spt7824 a/d converter is a 10-bit monolithic converter capable of word rates a minimum of 40 msps. on board track/hold function assures excellent dynamic performance without the need for external components. drive require- ment problems are minimized with an input capacitance of only 5 pf. inputs and outputs are ttl compatible to interface with ttl logic systems. an overrange output signal is provided to block diagram
spt 2 3/11/97 spt7824 electrical specifications t a =t min - t max , v cc =+5.0 v, v ee =-5.2 v, dv cc =+5.0 v, v in = 2.0 v, v sb =-2.0 v, v st =+2.0 v, f clk =40 mhz, 50% clock duty cycle, unless otherwise specified. test test spt7824a spt7824b parameters conditions level min typ max min typ max units resolution 10 10 bits dc accuracy (+25 c) full scale integral nonlinearity 100 khz sample rate v 1.0 1.5 lsb differential nonlinearity v 0.5 0.75 lsb no missing codes vi guaranteed guaranteed analog input f clk =1 mhz input voltage range v 2.0 2.0 v input bias current v in =0 v vi 30 60 30 60 m a input bias current t a =-55 to +125 civ 75 75 m a input resistance vi 100 300 100 300 k w input resistance t a =-55 to +125 c iv 75 300 75 300 k w input capacitance v 5 5 pf input bandwidth 3 db small signal v 120 120 mhz +fs error v 2.0 2.0 lsb -fs error v 2.0 2.0 lsb reference input f clk =1 mhz reference ladder resistance vi 500 800 500 800 w reference ladder tempco v 0.8 0.8 w / c timing characteristics maximum conversion rate vi 40 40 mhz overvoltage recovery time v 20 20 ns pipeline delay (latency) iv 1 1 clock cycle output delay t a =+25 c v 14 18 14 18 ns aperture delay time t a =+25 cv1 1ns aperture jitter time t a =+25 c v 5 5 ps-rms acquisition time t a =+25 c v 12 12 ns dynamic performance effective number of bits f in =1 mhz 8.7 8.2 bits f in =3.58 mhz 8.7 8.2 bits f in =10.0 mhz 7.3 6.9 bits absolute maximum ratings (beyond which damage may occur) 1 25 c note: 1. operation at any absolute maximum rating is not implied. see electrical specifications for proper nominal applied conditions in typical applications. supply voltages v cc ........................................................................... +6 v v ee ........................................................................... -6 v input voltages analog input ............................................... v fb v in v ft v ft , v fb .............................................................. +3.0 v, -3.0 v reference ladder current ..................................... 12 ma clk input .................................................................. v cc output digital outputs .......................................... +30 to -30 ma temperature operating temperature ............................ -55 to +125 c junction temperature 1 .............................................. +175 c lead temperature, (soldering 10 seconds) ........ +300 c storage temperature ................................ -65 to +150 c typical thermal impedances (unsoldered, in free air): 28l sidebrazed dip: q ja = 50 c/w, 28l plastic dip: q ja = 50 c/w, 28l soic: q ja = 100 c/w.
spt 3 3/11/97 spt7824 electrical specifications t a =t min -t max , v cc =+5.0 v, v ee =-5.2 v, dv cc =+5.0 v, v in = 2.0 v, v sb =-2.0 v, v st =+2.0 v, f clk =40 mhz, 50% clock duty cycle unless otherwise specified. test test spt7824a spt7824b parameters conditions level min typ max min typ max units dynamic performance signal-to-noise ratio (without harmonics) f in =1 mhz t a =+25 c i 55 57 52 54 db t a =0 to +70, -25 to +85 civ 5355 5052 db t a =-55 to +125 c* iv 49 51 46 48 db f in =3.58 mhz t a =+25 c i 55 57 52 54 db t a =0 to 70, -25 to +85 civ 5355 5052 db t a =-55 to +125 c* iv 49 51 46 48 db f in =10.0 mhz t a =+25 c i 48 50 46 48 db t a =0 to 70, -25 to +85 civ 4547 4345 db t a =-55 to +125 c* iv 41 43 39 41 db harmonic distortion f in =1 mhz t a =+25 c i 54 56 52 54 db t a =0 to 70, -25 to +85 civ 5153 4951 db t a =-55 to +125 c* iv 50 52 48 50 db f in =3.58 mhz t a =+25 c i 54 56 52 54 db t a =0 to 70, -25 to +85 civ 5153 4951 db t a =-55 to +125 c* iv 50 52 48 50 db f in =10.0 mhz t a =+25 c i 46 48 43 45 db t a =0 to 70, -25 to +85 civ 4547 4144 db t a =-55 to +125 c* iv 44 46 40 42 db signal-to-noise and distortion f in =1 mhz t a =+25 c i 52 54 49 51 db t a =0 to 70, -25 to +85 civ 49 46 db t a =-55 to +125 c* iv 48 45 db f in =3.58 mhz t a =+25 c i 52 54 49 51 db t a =0 to 70, -25 to +85 civ 49 46 db t a =-55 to +125 c* iv 48 45 db f in =10.0 mhz t a =+25 c i 44 46 41 43 db t a =0 to 70, -25 to +85 civ 43 40 db t a =-55 to +125 c* iv 40 37 db spurious free dynamic range t a =+25 c, f in =1 mhz v 67 67 db differential phase t a =+25 c, f in = 3.58 & 4.35 mhz v 0.2 0.2 degree differential gain t a =+25 c, f in = 3.58 & 4.35 mhz v 0.5 0.7 % digital inputs f clk =1 mhz logic 1 voltage vi 2.4 4.5 2.4 4.5 v logic 0 voltage vi 0.8 0.8 v maximum input current low t a =+25 c i 0 +5 +20 0 +5 +20 m a maximum input current high t a =+25 c i 0 +5 +20 0 +5 +20 m a pulse width low (clk) iv 10 10 ns pulse width high (clk) iv 10 300 10 300 ns digital outputs f clk =1 mhz logic "1" voltage vi 2.4 2.4 v logic "0" voltage vi 0.6 0.6 v power supply requirements voltages v cc iv 4.75 5.25 4.75 5.25 v dv cc iv 4.75 5.0 5.25 4.75 5.0 5.25 v -v ee iv -4.95 -5.2 -5.45 -4.95 -5.2 -5.45 v currents i cc t a =+25 c i 118 145 118 145 ma di cc t a =+25 c i 40 55 40 55 ma -i ee t a =+25 c i 40 57 40 57 ma power dissipation t a =+25 c i 1.0 1.3 1.0 1.3 w power supply rejection +5 v 0.25 v, -5.2 v 0.25 v v 1.0 1.0 lsb * temperature tested /883 only.
spt 4 3/11/97 spt7824 clk a a a a a output data t d t pwh a a a a a a a a a a a a a a a a n n+1 n+2 data valid n+1 data valid n n-2 n-1 t pwl t d aaaaaaaaaaa aaaaaaaaaaa data valid clk output data aa aa aa a a a test procedure 100% production tested at the specified temperature. 100% production tested at t a = +25 c, and sample tested at the specified temperatures. qa sample tested only at the specified temperatures. parameter is guaranteed (but not tested) by design and characterization data. parameter is a typical value for information purposes only. 100% production tested at t a = +25 c. parameter is guaranteed over specified temperature range. test level codes all electrical characteristics are subject to the following conditions: all parameters having min/max specifications are guaranteed. the test level column indi- cates the specific device testing actually per- formed during production and quality assur- ance inspection. any blank section in the data column indicates that the specification is not tested at the specified condition. test level i ii iii iv v vi figure 1a - timing diagram figure 1b - single event clock table i - timing parameters parameters description min typ max units t d clk to data valid prop delay - 14 18 ns t pwh clk high pulse width 10 - 300 ns t pwl clk low pulse width 10 - - ns
spt 5 3/11/97 spt7824 typical performance characteristics 50 20 30 40 60 70 80 10 0 10 1 10 2 thd vs input frequency input frequency (mhz) total harmonic distortion (db) fs = 40 msps input frequency (mhz) signal-to-noise ratio (db) snr vs input frequency 10 0 10 1 10 2 f s = 40 msps 30 40 50 60 70 20 80 a a a a a a a 20 30 40 50 60 70 80 10 0 10 1 10 2 snr, thd, sinad vs sample rate sample rate (msps) snr, thd, sinad (db) thd sinad f in = 1 mhz snr snr, thd, sinad vs temperature temperature (c) snr, thd, sinad (db) 45 50 55 60 65 40 f s = 40 msps f in = 1 mhz sinad thd snr -25 0 +25 +50 +75 signal-to-noise and distortion (db) 20 30 40 50 60 70 80 10 0 10 1 10 2 sinad vs input frequency input frequency (mhz) fs =40 msps -120 -90 -60 -30 0 input frequency (mhz) amplitude (db) spectral response 0 123456 78910 f s = 40 msps f in = 1 mhz
spt 6 3/11/97 spt7824 typical interface circuit the spt7824 requires few external components to achieve the stated operation and performance. figure 2 shows the typical interface requirements when using the spt7824 in normal circuit operation. the following section provides a description of the pin functions and outlines critical perfor- mance criteria to consider for achieving the optimal device performance. power supplies and grounding the spt7824 requires -5.2 v and +5 v analog supply voltages. the +5 v supply is common to analog v cc and digital dv cc . a ferrite bead in series with each supply line is intended to reduce the transient noise injected into the analog v cc . these beads should be connected as closely as pos- sible to the device. the connection between the beads and the spt7824 should not be shared with any other device. each power supply pin should be bypassed as closely as possible to the device. use 0.1 m f for v ee and v cc , and 0.01 m f for dv cc (chip caps are preferred). figure 2 - typical interface circuit agnd and dgnd are the two grounds available on the spt7824. these two internal grounds are isolated on the device. the use of ground planes is recommended to achieve optimum device performance. dgnd is needed for the dv cc return path (40 ma typical) and for the return path for all digital output logic interfaces. agnd and dgnd should be sepa- rated from each other and connected together only at the device through a ferrite bead. a schottky or hot carrier diode connected between agnd and v ee is required. the use of separate power supplies between v cc and dv cc is not recommended due to potential power supply sequencing latch-up conditions. using the recommended interface circuit shown in figure 2 will provide optimum device performance for the spt7824. d10 (overrange) d9 (msb) d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) d i g i t a l o u t p u t s - 5.2 v coarse a/d analog prescaler successive interpolation stage # 1 successive interpolation stage # n d e c o d i n g n e t w o r k 4 ic1 (ref-03) 6 5 2 4 + 5 v + v out tr i m gnd v in 1 f c1 .01 f + - 10 k w 1 32 4 8 7 6 10 k w 30 k w 30 k w c19 1 f + +5 v .01 f .01 f clk v in v ft v st v rm v sb v fb r 2r 2r 2r 2r r + 1 f clk v in ic2 op-07 v ee v cc dv cc v ee v cc dv cc agnd dgnd dgnd agnd 10 f 10 f + d1 c10 .01 f + (ttl) (2 v) +2.5 v -2.5 v fb +5 v agnd dgnd -5.2 v (analog) (analog) fb fb c11 .01 f r1 100 w 2.5 v max c2 .01 f c3 .01 f c4 .01 f c5 .01 f c6 .1 f c7 .1 f c8 c9 notes to prevent latch-up due to power sequencing: 1) d1 = schottky or hot carrier diode, p/n in5817. 2) fb = ferrite bead, fair rite p/n 2743001111 to be mounted as close to the device as possible. the ferrite bead to the adc connection should not be shared with any other device. 3) c1-c11 = chip cap (recommended) mounted as close to the device's pin as possible. 4) use of a separate supply for v cc and dv cc is not recommended. 5) r1 provides current limiting to 45 ma. 6) c6, c7, c8 and c9 should be ten times larger than c10 and c11. 7) c8 = c9 = a 0.1 f cap in parallel with a 4.7 f cap.
spt 7 3/11/97 spt7824 voltage reference the spt7824 requires the use of two voltage references: v ft and v fb . v ft is the force for the top of the voltage reference ladder (+2.5 v typ), v fb (-2.5 v typ) is the force for the bottom of the voltage reference ladder. both voltages are applied across an internal reference ladder resistance of 800 ohms. the +2.5 v voltage source for reference v ft must be current limited to 20 ma maximum if a different driving circuit is used in place of the recommended reference circuit shown in figures 2 and 3. in addition, there are three reference ladder taps (v st , v rm and v sb ). v st is the sense for the top of the reference ladder (+2.0 v), v rm is the midpoint of the ladder (0.0 v typ) and v sb is the sense for the bottom of the reference ladder (-2.0 v). the voltages seen at v st and v sb are the true full scale input voltages of the device when v ft and v fb are driven to the recommended voltages (+2.5 v and -2.5 v typical respectively). these points should be used to monitor the actual full scale input voltage of the device and should not be driven to the expected ideal values as is commonly done with standard flash converters. when not being used, a decoupling capacitor of .01 uf (chip carrier preferred) connected to agnd from each tap is recommended to minimize high frequency noise injection. figure 3 - analog equivalent input circuit ever, because the device is laser trimmed to optimize perfor- mance with 2.5 v references, the accuracy of the device will degrade if operated beyond a 2% range. the following errors are defined: +fs error = top of ladder offset voltage = d (+fs -v st +1 lsb) -fs error = bottom of ladder offset voltage = d (-fs -v sb -1 lsb) where the +fs (full scale) input voltage is defined as the output transition between 1-10 and 1-11 and the -fs input voltage is defined as the output transition between 0-00 and 0-01. analog input v in is the analog input. the full scale input range will be 80% of the reference voltage or 2 v with v fb =-2.5 v and v ft =+2.5 v. the drive requirements for the analog inputs are minimal when compared to conventional flash converters due to the spt7824s extremely low input capacitance of only 5 pf and very high input resistance of 300 k w . for example, for an input signal of 2 v p-p with an input frequency of 10 mhz, the peak output current required for the driving circuit is only 628 m a. clock input the spt7824 is driven from a single-ended ttl input (clk). the clk pulse width (tpwh) must be kept between 10 ns and 300 ns to ensure proper operation of the internal track-and- hold amplifier. (see timing diagram.) when operating the spt7824 at sampling rates above 3 msps, it is recom- mended that the clock input duty cycle be kept at 50% to optimize performance. (see figure 4.) the analog input signal is latched on the rising edge of the clk. the clock input must be driven from fast ttl logic (v ih 4.5 v, t rise <6 ns). in the event the clock is driven from a high current source, use a 100 w resistor in series to current limit to approximately 45 ma. figure 4 - snr vs clock duty cycle v cc v ee v ft v in a a a a a a a a analog prescaler an example of a reference driver circuit recommended is shown in figure 2. ic1 is ref-03, the +2.5 v reference with a tolerance of 0.6% or +/- 0.015 v. the potentiometer r1 is 10 k w and supports a minimum adjustable range of up to 150 mv. ic2 is recommended to be an op-07 or equivalent device. r2 and r3 must be matched to within 0.1% with good tc tracking to maintain a 0.3 lsb matching between v ft and v fb . if 0.1% matching is not met, then potentiometer r4 can be used to adjust the v fb voltage to the desired level. v ft and v fb should be adjusted such that v st and v sb are exactly +2.0 v and -2.0 v respectively. the analog input range will scale proportionally with respect to the reference voltage if a different input range is required. the maximum scaling factor for device operation is 20% of the recommended reference voltages of v ft and v fb . how- 30 35 40 45 50 55 60 65 70 75 duty cycle duty cycle of positive clock pulse (%) signal-to-noise ratio (db) a a a a a a 43 45 47 49 51 53 55 57 59 tpwl tpwh = t pwh t pwl a a a
spt 8 3/11/97 spt7824 digital outputs the format of the output data (d0-d9) is straight binary. (see table ii.) the outputs are latched on the rising edge of clk with a propagation delay of 14 ns (typ). there is a one clock cycle latency between clk and the valid output data. (see timing diagram.) table ii - output data information analog input overrange output code d1o d9-do >+2.0 v + 1/2 lsb 1 11 1111 1111 +2.0 v -1 lsb o 11 1111 111? 0.0 v o ?? ???? ???? -2.0 v +1 lsb o oo oooo ooo? <-2.0 v o oo oooo oooo (? indicates the flickering bit between logic 0 and 1). the rise times and fall times of the digital outputs are not symmetrical. the propagation delay of the rise time is typi- cally 14 ns and the fall time is typically 6 ns. (see figure 5.) the nonsymmetrical rise and fall times create approximately 8 ns of invalid data. overrange output the overrange output (d10) is an indication that the analog input signal has exceeded the positive full scale input voltage by 1 lsb. when this condition occurs, d10 will switch to logic 1. all other data outputs (d0 to d9) will remain at logic 1 as long as d10 remains at logic 1. this feature makes it possible to include the spt7824 into higher resolution systems. evaluation board the eb7824 evaluation board is available to aid designers in demonstrating the full performance of the spt7824. this board includes a reference circuit, clock driver circuit, output data latches and an on-board reconstruction of the digital data. an application note describing the operation of this board as well as information on the testing of the spt7824 is also available. contact the factory for price and availability. figure 5 - digital output characteristics 3.5 v n+1 rise time 6 nsec 6 ns typ. clk in n 2.4 v invalid data (n-1) (n-2) (n-1) data out (equivalent) invalid data aaa aaa aaa aaa aaa aaa data out (actual) (n-2) (n-1) (n) 2.4 v 0.8 v 0.5 v tpd1 (14 ns typ.) aaa aaa aaa aaa invalid data invalid data
spt 9 3/11/97 spt7824 package outlines 28-lead sidebrazed inches millimeters symbol min max min max a 0.077 0.093 1.96 2.36 b 0.016 0.020 0.41 0.51 c 0.095 0.105 2.41 2.67 d .050 typ 0.00 1.27 e 0.040 0.060 1.02 1.52 f 0.215 0.235 5.46 5.97 g 1.388 1.412 35.26 35.86 h 0.585 0.605 14.86 15.37 i 0.009 0.012 0.23 0.30 j 0.600 0.620 15.24 15.75 a b c d e f g 1 28 i h j 28-lead plastic dip inches millimeters symbol min max min max a 0.200 5.08 b 0.120 0.135 3.05 3.43 c 0.020 0.51 d 0.100 2.54 e 0.067 1.70 f 0.013 0.33 g 0.170 0.180 4.32 4.57 h 0.622 15.80 i 0.555 14.10 j 1.460 37.08 k 0.085 2.16 a b c d e 1 28 j k f g h i
spt 10 3/11/97 spt7824 package outlines 28-lead soic inches millimeters symbol min max min max a 0.696 0.712 17.68 18.08 b 0.004 0.012 0.10 0.30 c .050 typ 0.00 1.27 d 0.014 0.019 0.36 0.48 e 0.009 0.012 0.23 0.30 f 0.080 0.100 2.03 2.54 g 0.016 0.050 0.41 1.27 h 0.394 0.419 10.01 10.64 i 0.291 0.299 7.39 7.59 1 28 a b cd e f g i h
spt 11 3/11/97 spt7824 pin assignments dgnd d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 1 2 3 4 5 6 7 8 9 10 11 12 v in v sb clk agnd v st v cc v ee v ft dgnd dv 13 14 v rm 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v v agnd v ee cc fb dv cc cc dip/pdip/soic pin functions name function dgnd digital ground d0-d9 ttl outputs (d0=lsb) d10 ttl output overrange clk clock v ee -5.2 v supply (analog) agnd analog ground v cc +5.0 v supply (analog) v in analog input dv cc digital +5.0 v supply v rm middle of voltage reference ladder v ft force for top of reference ladder v st sense for top of reference ladder v fb force for bottom of reference ladder v sb sense for bottom of reference ladder part number temperature range package type spt7824aij -25 to +85 c 28l sidebrazed dip SPT7824BIJ -25 to +85 c 28l sidebrazed dip spt7824acn 0 to +70 c 28l plastic dip spt7824bcn 0 to +70 c 28l plastic dip spt7824acs 0 to +70 c 28l soic spt7824bcs 0 to +70 c 28l soic spt7824amj -55 to +125 c 28l sidebrazed dip spt7824bmj -55 to +125 c 28l sidebrazed dip ordering information signal processing technologies, inc. reserves the right to change products and specifications without notice. permission is hereby expressly granted to copy this literature for informational purposes only. copying this material for any other use is strictly prohibited. warning - life support applications policy - spt products should not be used within life support systems without the specific written consent of spt. a life support system is a product or system intended to support or sustain life which, if it fails, can be reasonably expected to result in significant personal injury or death. signal processing technologies believes that ultrasonic cleaning of its products may damage the wire bonding, leading to device failure. it is therefore not recommended, and exposure of a device to such a process will void the product warranty.

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